Bartosz Matwiejczyk

1.ASIC Emulation Platform based on Synopsys HAPS systems, FPGA backend, TDM development, Clock & Reset topology.

2.ASIC Emulation Platform based on ALTERA Stratix II EP2S180 devices (Design Leader) – preparing RTL for FPGA implementation; replacing ASIC process library components with ALTERA components; preparing simulation macros (bash, awk), partitioning RTL to fit large designs in to multi FPGA platforms

3.Schematic entry of Coprocessor Cards for Intel IXP2800 network processor based on Virtex 2 and Virtex Pro devices using QDR II interface

4.Implementation 3GPP ciphering algorithms for UMTS systems in to FPGA structures - Virtex 2 and Virtex Pro devices

5.Implementation of QDR II memory interface in to FPGA structures - Virtex 2 and Virtex Pro device

6.Software test environment (Verilog PLI Mechanism) for testing 3GPP ciphering algorithms for UMTS systems (custom DLL libraries written in C++ integrated with ModelSim and ActiveHDL simulators, graphic user interface - MFC)